Technical Field
The present disclosure relates to an electronic device provided with an encapsulation structure with improved electric accessibility and to a method of manufacturing the electronic device.
Description of the Related Art
As is known, in the manufacture of semiconductor devices, encapsulation or packaging is the final step that converts a semiconductor substrate into a functional component that may be mounted on a printed circuit board (PCB). Typically, the semiconductor substrate is in the form of a semiconductor die. The package provides a protection for the semiconductor die and provides the necessary electrical connections, through which it is possible to supply signals to the semiconductor die and acquire signals coming from the semiconductor die.
To meet the specifications for an increasingly greater integration and reduction in size, the packaging methods currently used include die-level or wafer-level packaging (WLP) and 3D packaging. Further solutions envisage surface-mount devices (SMDs), which enable further reduction in the dimensions of the package and costs of assembly. Consider, for example, the package known as PowerFlat™. This type of package enables minimization of the space occupied by the package itself when mounted on the PCB and at the same time increase of the heat exchange with the PCB itself through the metal connections between the bottom part of the package and the PCB. In fact, as illustrated by way of example in FIG. 1, the electrical connections are obtained by flat regions extending along a bottom surface of the package. With reference to FIG. 1, the package is identified by the reference number 1. A structure 2 that constitutes a support for a die 3 and is designed to provide the electrical connections between the die 3 and the outside of the package 1, is known as a “leadframe” and extends in such a way that a bottom surface region 2b thereof lies in the same plane as a bottom surface 1b of the package 1, thus constituting itself a part of the bottom surface 1b of the package 1. The die 3 is bonded (e.g., by a layer of glue 4) to a top surface region 2a of the leadframe 2. This top surface region 2a has a flat surface expressly dedicated to coupling with the die 3, better known as a “die-attach pad”. The top surface region 2a of the leadframe 2 is opposite to the bottom surface region 2b of the leadframe 2.
The leadframe 2 makes available, on the bottom surface region 2b, a plurality of electrical-contact regions 5a, 5b, which are electrically insulated from one another and each of which is designed to transfer a signal from and/or to the PCB. For instance, if the die 3 provides a MOS transistor, the electrical-contact region 5a will be, for example, electrically coupled to the source region S of the MOSFET, whereas the electrical-contact region 5b will be, for example, electrically coupled to the drain region D of the MOS transistor. A further electrical contact (not illustrated) has to be provided, in this example, to form the gate electrical contact.
A layer of resin 7, in particular epoxy resin, extends over the top surface region 2a of the leadframe 2, to cover and protect the die 3, and is designed to protect the top electrical insulation of the leadframe 2 and of the die 3. The resin 7 further extends in perforated areas of the leadframe 2, until it reaches the plane formed by the bottom surface region 2b and thus completes formation of the bottom surface 1b of the package 1.
Since the electrical-contact regions 5a, 5b both extend in the bottom surface 1b of the package 1, electrical coupling with the PCB (not illustrated herein) is obtained at the bottom surface 1b of the package 1. In general, the entire bottom surface region 2b of the leadframe 2 is designed to be set facing the PCB, and thus it likewise provides a surface for heat exchange between the package 1 and the PCB.
Current packages, and in particular the package described with reference to FIG. 1, present certain disadvantages. In particular, for power applications the heat exchange that is obtained with the PCB may not be sufficient to protect a good cooling of the die 3. Furthermore, the operations for testing the package 1 prove complex and costly, in so far as they may be carried out by providing a PCB dedicated to the testing procedure, to which the package 1 is to be coupled by bonding of the bottom surface 1b. 